State-of-the-art Space Upstream Technologies

Payload Data Processing Units and High-Speed Hardware Accelerators

FPGA/ASIC/IP Cores for Defense and Space Applications

About DSCAL

The Digital Systems and Computer Architecture Laboratory (DSCAL) of the National and Kapodistrian University of Athens (NKUA) is at the forefront of space upstream technology development.

Our research team consists of faculty members and researchers from the School of Science, specifically from the Department of Informatics and Telecommunications and the Department of Aerospace Science and Technology.

Our Focus

DSCAL serves the educational, research, and developmental needs of NKUA's School of Science, focusing on the design and architecture of computing systems, as well as the interactions between hardware and software in terms of performance, energy/power consumption, and reliability for high-performance embedded systems.

The research team's activities are focused on the development of On-board Data Systems, with an emphasis on Payload Data Processing, having participated in major institutional space missions of the European Space Agency (ESA) since 2009.

TRL-9
Technology Readiness Level
From PROBA-3 Mission
15+
Years Experience
In Space Upstream Applications
5+
ESA Missions
Active Participation
3+
Million Euros Funding
In Space Upstream Activities

Our Vision

"Create a Center of Excellence in Space Upstream Technology Designed in Greece"

The NKUA-DSCAL research team can provide cutting-edge technologies and products to the global industry, including Payload Data Processing Units and hardware accelerator IP cores for FPGA/ASIC technologies, implementing standards of the Consultative Committee for Space Data Systems (CCSDS).

Leadership Team

Academic personnel leading innovation in space technology Designed in Greece

Professor Antonios Paschalis

Professor Antonios Paschalis

Antonios Paschalis is Professor at the Department of Informatics & Telecommunications of the National and Kapodistrian University of Athens (NKUA), Director of the Digital Systems & Computer Architecture Laboratory (DSCAL), co-Founder and Director of the Inter-Institutional Master Studies Program at Space Technologies, Applications and seRvices (STAR), co-Founder and Director of the Common Master Studies Program with the Greek Army at Secure Telecommunications and Network Systems, member of the former Temporal Assembly of the Department of Aerospace Science and Technology of the NKUA, academic member of the Steering Committee of the Hellenic innovation ecosystem in the field of space technologies and applications (si-Cluster), member of the Board of the former Hellenic Space Agency (HSA), and Chairman of the Department of Informatics & Telecommunications of the NKUA for 4 years (2016-2020).

Prof. Paschalis has participated in all phases of ESA space missions: PROBA-3 since 2009 and TRUTHS since 2021 delivering state-of-the-art space technologies for on-board image data compression. Under his leadership, the research group in space upstream technology of DSCAL innovates worldwide in the development in Greece of Payload Data Processing Units and High-Speed Hardware Accelerators, as IP cores in SoC FPGA technology, for all data, 2D and 3D (hyperspectral) image compression algorithms, channel-coding & synchronization algorithms and authentication & encryption algorithms, that satisfy the CCSDS space standards 121, 122, 123, 131, 142 and 352, and constitute a High-Speed Data Chain for "smart" next-generation payloads for EO and optical/RF communication.

Prof. Paschalis participates as Deputy Project Manager and PA/QA Manager and co-I in the ERMIS - Hellenic CubeSat Demonstration Mission with prime contractor the National and Kapodistrian University of Athens that aims to develop in Greece 3 nanosatellites (6U-8U CubeSat type) under the Greek National Satellite Space Programme in order to demonstrate pilot activities like 5G-IoT communication services, RF inter-satellite link, optical laser link, hyperspectral EO applications, ADCS, OBC, Payload Data Processing Units and hardware accelerators of CCSDS algorithms, ground segment capabilities and skills, all unique to Greece and Europe.

Prof. Paschalis was born in 1960, he received the B.Sc. degree in Physics in 1982, the M.Sc. degree in Electronic Automation in 1985 and the Ph.D. in Dependable Computers, under scholarship from the NCSR "Demokritos" in 1987, all from the Department of Physics of the National and Kapodistrian University of Athens. He has about 40 years of experience in the development of fault-tolerant systems, 30 years of experience in self-testing of VLSI circuits and Systems on Chip and 15 years of experience in the design and architecture of high-performance on-board payload data processing units for space applications. He has published more than 160 scientific publications; he is co-author of a book and he holds a US patent (5.960.009). He has supervised 9 graduated Ph.D. students, 5 of them are Professors in Academia. Currently, there are more than 3,100 citations that refer to his published material and his h-index is 34. He is Golden Core Member of the IEEE Computer Society.

Professor Nektarios Kranitis

Professor Nektarios Kranitis

Nektarios Kranitis currently serves as a Professor and Deputy Head of the Department of Aerospace Science and Technology, NKUA. He has more than 25 years of experience in the development of FPGA systems, more than 10 years of experience in the development of on-board computers & data handling, on-board payload data processing systems, IP Core based hardware acceleration, and dependable and reliable systems design. He has more than 10 years of experience in design, development, verification and validation of microelectronics compliant with ECSS-Q-ST-60-02C standard. He was awarded a scholarship for doctoral studies from the National Centre for Scientific Research (N.C.S.R.) "Demokritos".

Professor Kranitis has been involved as proposal writer, PI or senior researcher in several R&D projects funded by ESA, EU and the Greek government in onboard data systems technology. He has developed cutting-edge technology hardware accelerators as IP Cores for monoband images (CCSDS 122), hyperspectral images (CCSDS 123) and data compression (CCSDS 121), channel coding for near-earth (C2) and deep-space (AR4JA) applications (CCSDS 131), and authenticated encryption (CCSDS 352 AES/GCM), providing state of-the-art data-rate performance.

He participates in Phase C/D/E1 of ESA PROBA-3 space mission in the development of onboard data processing FPGA firmware of the ASPIICS Coronagraph System Payload as WP Manager for the Image Data Compression IP Core NRE. He also participates in Phase A/B1/B2/Advanced C for On-Board Compression activities for ESA TRUTHS mission. He participated in the development and demonstration of next-generation on-board data handling technologies in collaboration with AIRBUS DS and DLR in the framework of H2020 Hi-SIDE project (GA 776151), managed by HaDEA, which won the 'Innovation in Space Award 2022' at the European Space Forum 2022. He participates as Onboard Payload Data Processing Expert in 2 CubeSat missions, ERMIS and Hellenic Space Dawn (HSD), in the framework of ESA AO/1-11498/22/UK/ND Greek CubeSats In-Orbit Validation Projects. He also participates to the ESA/Greek National Satellite Space Project Axis 1.2 (radar program) developing SAR raw data compression solutions.

He was awarded a very competitive post-doctoral research grant (180k€), serving as Principal Investigator (PI), funded by Hellenic Foundation for Research & Innovation (H.F.R.I) – ELIDEK for developing state-of-the-art hardware accelerator IP Cores for onboard data systems. He has published more than 80 scientific publications in highly cited and peer reviewed transactions, journals and conference proceedings. Currently, there are more than 1700 citations that refer to his published work while his h-index is 23. He is a Senior Member of the IEEE and the IEEE Aerospace and Electronic Systems Society (AESS) and the IEEE Computer Society (CS).

Core Business & Expertise

ESA Technology Tree: On-Board Data Subsystems Domain

Payload Data Processing

System, HW, SW, FW, Technologies since 2010

System-On-Chip (SoC) Dependable and Adaptable Payload Data Processing Units (PDPU)

Hardware Accelerators

ASIC/FPGA/IP Core technology development according to:

  • ECSS-Q-ST-60-02C
  • ECSS-E-ST-20-40C

High-Speed Data Chain

For "smart" next-generation payloads for Earth Observation and optical/RF communication

FDIR

Fault Detection, Isolation and Recovery for mission-critical systems

Space Technology Heritage

TRL-9 (2024)

Flight-proven technology from Space Missions

Technical Infrastructure

🔧

FPGA development boards (Zynq, Virtex-7, Ultrascale+) and GOMSpace Nanomind MK3 HP/SDR

💻

Workstations with state-of-the-art EDA CAD tools from AMD/Xilinx, Synopsys, Mentor Graphics and Microchip Technology

📊

2GHz Mixed Signal Oscilloscope with 8-analog & 64-digital channels, power supplies, etc.

🔌

End-to-end validation with SpaceFibre (ECSS-E-ST-50-11C) & SpaceWire (ECSS-E-ST-50-12C) Tester

Space Missions

Mature Space Upstream Technology in ESA and National Space Missions

TRL-9 • Flight Heritage
ESA PROBA-3
Phases A/B/C/D/E1 Launch 12/2024 Mission Completed Successfully

Scope: Develop and demonstrate in-orbit formation flying of two spacecrafts and provide scientific data using the giant coronagraph system (ASPIICS) for observation of the sun corona.

DSCAL Contribution: Image Data Compression Algorithm and HW accelerator (IP core in FPGA technology) based on CCSDS 121 Lossless Data Compression enhanced for 2D coronagraph images.

Achievement: Flight heritage, TRL=9 @ 2024

CCSDS 121 Lossless Compression FPGA IP Core Formation Flying
TRL-4 • Active Development

ESA TRUTHS

2021-2026
ESA TRUTHS Mission Satellite
Phase A/B1 Extended to Phases B2/Advanced C

Focus: System Feasibility Studies for On-Board Compression

Implementation: CCSDS 123.0-B-2 Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Compression algorithm

Collaboration: Participation in PPU implementation with ISD and AIRBUS

CCSDS 123.0-B-2 Hyperspectral Compression AIRBUS Partnership
Active • 2024-2026

Greek National Space Programme

2024-2026

Participation: 4+ additional missions of the National Space Program

Focus Area: Axis 1.2 (radar program) - Developing novel SAR raw data compression solutions

SAR Compression National Program

Technology Portfolio

State-of-the-art competitive HW accelerators, as IP Cores - Designed in Greece

CCSDS - Consultative Committee for Space Data Systems Logo

Portfolio of cutting-edge hardware accelerator IP Cores targeting space-grade (V5QV, KU060, RTG4) and COTS (Zynq 7000) FPGAs, implementing CCSDS recommended standards.

CCSDS 123.0-B-1/2

Flight Heritage

Lossless/Near Lossless Multi-/Hyperspectral Image Compression

CCSDS 123 Hyperspectral Compression Standard

Novel parallel and scalable architecture with double performance than ESA IP core

  • Novel SAR compression capability
  • Flight heritage from ERMIS mission
  • Best-in-class performance
4.56 Gbps Single Core @ 1.67W
25.44 Gbps Six Cores @ 6.12W

CCSDS 122.0-B-1

Flight Heritage

Image Data Compression

CCSDS 122 Image Data Compression Standard
  • Deep lossy compression (<1.5 bpp)
  • Rate-limited capability
  • Mission-proven reliability

CCSDS 122.1

World's First

Transform based Multi-/Hyperspectral Image Compression

CCSDS 122.1 Transform-based Compression Standard

World's first implementation of this advanced compression standard

  • Spectral transform capability
  • Integer Wavelet Transform (5-stage CDF 5/3)
  • Reverse Water Filling rate allocation

CCSDS 121.0-B-2

TRL-9

Lossless Data Compression

CCSDS 121 Lossless Data Compression Standard

Flight heritage from PROBA-3 mission

  • Proven in ESA mission
  • Enhanced for 2D coronagraph images
  • Maximum reliability

CCSDS 131.1-O-2

Best Performance

Low-Density Parity-Check (LDPC) codes

CCSDS 131 LDPC Channel Coding Standard

C2 and AR4JA codes with industry-leading performance

  • Near-Earth high data-rates
  • Deep-Space very low SNR
  • Small footprint design

CCSDS 131.5-O-1

World's First

Packet-Level Erasure Coding

CCSDS 131.5 Packet-Level Erasure Coding Standard

World's first implementation of this emerging standard

  • Packet-level protection
  • Enhanced reliability
  • Pioneer implementation

CCSDS 142.0-B-2

Flight Heritage

O3K LDPC Channel Coding

CCSDS 142 O3K LDPC Channel Coding Standard

Much less footprint than ESA IP core, flight heritage from ERMIS mission

  • Optical communication optimized
  • ARA & PBRL LDPC codes
  • Integrated with ERMIS Optical Terminal

CCSDS 352.0-B-2

Secure

Cryptographic Algorithms AES-GCM 256

CCSDS 352 AES-GCM Cryptographic Standard

Competitive design for authenticated encryption

  • AES-GCM 256-bit encryption
  • Authentication & encryption
  • Mission-critical security

Major Research Projects

2014-2015

EXCELLENCE-II

SCORPIUS-5149

"Single-Chip Radiation Tolerant Dynamically Reconfigurable Payload Data Processing Units for Future Space Applications"

DSCAL PI
2018-2022

Research-Create-Innovate

SYSYFOS - "High-performance and High-reliability Compression and Management of Hyperspectral Image Data"

First implementation of CCSDS 122.1 Hyperspectral Compression in the World!
DSCAL PI
2018-2021

H.F.R.I – ELIDEK Postdoctoral Research Grant

"Renata: Next Generation Hardware Accelerated Onboard Hyperspectral Data Handling"

First implementation of CCSDS 123.0-B2 Hybrid Encoder in the World!
DSCAL PI
ESA Contract

ESA Contract No. 4000136723/22/NL/CRS

"CCSDS 123.0-B-2 Lossless/lossy multispectral & hyperspectral compression IP core"

CCSDS 123.0-B2 Hybrid Encoder, as IP Core, available from ESA for future space missions

ESA

Publications

Selected peer-reviewed publications in leading journals

2015

An Efficient FPGA Implementation of CCSDS 121.0-B-2 Lossless Data Compression algorithm for Image Compression

N. Kranitis, I. Sideris, A. Tsigkanos, G. Theodorou, A. Paschalis, R. Vitulli

Journal of Applied Remote Sensing (JARS), Volume 9, Issue 1, Special Issue on Onboard Compression and Processing for Space Data Systems, May 2015

JARS
2020

Efficient Architectures for Multigigabit CCSDS LDPC Encoders

D. Theodoropoulos, N. Kranitis, A. Tsigkanos, A. Paschalis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 5, pp. 1118-1127, May 2020

IEEE T-VLSI
2020

A 13.3 Gbps 9/7M Discrete Wavelet Transform for CCSDS 122.0-B-1 Image Data Compression on a Space-Grade SRAM FPGA

E. Machairas, N. Kranitis

MDPI Electronics, Special Issue "Hardware Architectures for Real Time Image Processing", 2020, 9(8), 1234

Electronics
2020

High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1

A. Tsigkanos, N. Kranitis, D. Theodoropoulos, A. Paschalis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 11, pp. 2397-2409, Nov. 2020

IEEE T-VLSI
2021

A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA

A. Tsigkanos, N. Kranitis, G. Theodorou, A. Paschalis

IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 1, pp. 90-103, 1 Jan.-March 2021

IEEE TETC
2022

Efficient Hardware Architectures and Implementations of Packet-Level Erasure Coding Schemes for High Data Rate Reliable Satellite Communications

D. Theodoropoulos, N. Kranitis, A. Tsigkanos, E. Machairas, A. Paschalis

IEEE Transactions on Aerospace and Electronic Systems, vol. 58, no. 3, pp. 2269-2280, June 2022

IEEE T-AES
2022

An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology

P. Chatziantoniou, A. Tsigkanos, D. Theodoropoulos, N. Kranitis, A. Paschalis

IEEE Transactions on Aerospace and Electronic Systems, vol. 58, no. 6, pp. 5470-5482, Dec. 2022

IEEE T-AES

Recent & Current Collaborations

Partnering with leading organizations in space technology

AIRBUS Defence & Space

Development of on-board hyperspectral image compression subsystems for next-generation satellites

EU HORIZON Hi-SIDE project

EU Horizon 2020 Programme Logo Innovation in Space Award 2022 at European Space Forum

ISD & AIRBUS UK

Development of the Payload Processing Unit for the TRUTHS mission

ESA institutional mission

European Space Agency Logo

ICEYE

Development of novel hardware accelerators for SAR compression

Integration in next generation SAR satellites (National Space Program)

ISD - 5G Channel Coding

Hardware accelerators for 5G channel coding for Ship Structural Health Monitoring

EDF/DEFIS

European Defence Fund Logo

ISD - RF System-on-Chip

Novel hardware accelerators for critical channel-coding in European RF SoC for D&S applications

EDF/DEFIS

European Defence Fund Logo

ISD - AI Accelerators

Novel AI-based hardware accelerators for vessel detection

EU HORIZON NeAIxt project

EU Horizon 2020 Programme Logo
DSCAL International Collaborations Network

Contact Us!

Address

National and Kapodistrian University of Athens

Dept. of Informatics and Telecommunications

Panepistimiopolis, Ilissia

Athens 15784

Phone

Prof. Antonios Paschalis

+30 210 727 5231

Prof. Nektarios Kranitis

+30 222 802 1903

E-Mail

Prof. Antonios Paschalis

paschalis@di.uoa.gr

Prof. Nektarios Kranitis

nkran@aerospace.uoa.gr

Our Commitment

"Provide the European space supply chain with products and services as Center of Excellence in On-Board Data Subsystems domain"

Create Payload Data Processing Units and a Portfolio of State-of-the-art competitive HW accelerators, as IP Cores implemented in space-grade and COTS FPGAs in accordance to CCSDS recommended standards.