Email: nkran at di dot uoa dot gr
Phone: +30 210 7275222
Mailing Address:
National and Kapodistrian University of Athens, Dept. of Informatics and Telecommunications, Panepistimiopolis, Ilissia, Athens 15784, Greece

• Hellenic Foundation for Research & Innovation (H.F.R.I) – ELIDEK Postdoctoral Research Grant to Dr. Nektarios Kranitis (Coordinator), “Next Generation Hardware Accelerated Onboard Hyperspectral Data Handling”, 2018-2021, Total Budget: 180,000 euro (ranking 25th/308 proposals in Engineering and Technology Sciences)
• Invited Book Chapter in “Processor Design. System-On-Chip Computing for ASICs and FPGAs”, J.Nurmi (Editor), Springer, June 2007, ISBN 978-1-4020-5529-4. The invited book chapter is about the research work of my Doctoral Dissertation. Other chapters are authored by top processor industry companies including Intel, Tensilica, Texas Instruments, Altera, STMicroelectronics
• Best paper award nomination at the ACM/IEEE Design, Automation and Test in Europe (DATE’03) Conference. Paper was invited by DATE’03 Program Chair for publication at the IEE Proceedings-Computers and Digital Techniques, DATE’03 Special Issue, among 11 other papers out of 152 DATE’03 papers (Top 1.8%)
• The IEEE VLSI Test Symposium (VTS‘02) paper was ranked among the Top 15% of all VTS ‘02 submissions and was invited by VTS’02 Program Chair for publication at the Journal of Electronic Testing: Theory and Applications (JETTA), VTS’02 Special Issue. The paper was the only European paper present in the Special Issue
• Scholarship for PhD studies (4 years), Institute of Informatics and Telecommunications, National Centre for Scientific Research (N.C.S.R.) “Demokritos”

He is an expert technical proposal writer having received more than 1,536,000 € in research grants. He has more than 10 years of experience in EU and National funded research projects (proposal writing, WP manager, technical project manager, senior researcher) including the following: 

• “Single-Chip Radiation Tolerant Dynamically Reconfigurable Payload Data Processing Units for Future Space Applications”, ARISTEIA-II, GSRT, (2014-2015), 236,000€ (Principal Engineer)
• “Data-Intensive Space Applications on Emerging Massively Parallel Processor Architectures: Performance, Energy, and Dependability Opportunities”, Greek-China Research Collaboration, GSRT, (2013-2015), 210,000€ (FPGA Accelerator Expert Consultant for HAI)
• ESA PROBA-3 mission ASPIICS Coronagraph System Phase B/C/D/E1 (2009-2020), (WP manager, Principal Engineer)
• “High-performance and High-reliability Compression and Management of Hyperspectral Image Data”, RESEARCH-CREATE-INNOVATE, GSRT (2018-2021), 900,000€ (Technical Project Manager for NKUA activities)
• Hi-FLY (High-Speed Integrated Satellite Data Systems For Leading EU IndustrY), H2020-COMPET-3-2017 High speed data chain (2018-2021), 7,000,000€ (Technical Project Manager for NKUA activities)
• “Next Generation Hardware Accelerated Onboard Hyperspectral Data Handling”, Hellenic Foundation for Research & Innovation (H.F.R.I) – ELIDEK Postdoctoral Research Grant to Dr. Nektarios Kranitis (Coordinator), 2018-2021, 180,000 euro (ranking 25th/308 proposals in Engineering and Technology Sciences)

Undergraduate courses (Dept. of Informatics & Telecommunications, University of Athens, Greece)

• Computer Architecture I (Fall 2005, Fall 2006, Fall 2007, Fall 2008, Fall 2009, Fall 2010)
• Computer Architecture II (Spring 2006, Spring 2007, Spring 2008, Spring 2009, Spring 2010, Spring 2011)
• Logic Design Lab (Fall 2016, Fall 2017)
• Embedded Systems (Spring 2014)

Postgraduate courses (Dept. of Informatics & Telecommunications, University of Athens, Greece)

• Advanced Computer Architecture (Spring 2008, Spring 2009, Spring 2010, Spring 2011)
• Advanced Design of Digital Systems (Spring 2007, Spring 2008, Spring 2014, Spring 2015, Spring 2016, Spring 2017, Spring 2018)

PhD in Computer Science (2005) Dept. of Informatics & Telecommunications, University of Athens
Thesis title: “Effective Software-Based Self-Test Techniques for Processors”
Thesis advisor: Professor Antonis Paschalis
BSc in Physics (1997) Dept. of Physics, University of Patras, Greece

• Dependable Computer Architecture
• FPGA-based Hardware Acceleration 
• On-Board Computers & Data Handling
• On-Board Payload Data Processing Systems
• Embedded Digital Systems Design, Test and Fault Tolerance
• Microprocessor and Embedded Processor-based Systems Reliability
• Low-cost, power-aware On-Line Defect Detection

My main research activities are in the area of Dependable Computer Architecture. Given the inherent redundancy of contemporary and future processor architectures and the existence of low-cost mechanisms for system recovery and repair, the remaining dependable computer architecture major challenge in the design of defect-tolerant processor architectures is the development of low-cost defect detection techniques. By leveraging the power of the processor Instruction Set Architecture (ISA) and internal processor resources, i have introduced in my doctoral dissertation a methodology (Software-Based Self-Test, SBST) that enables low-cost, non-intrusive, on-line defect detection and manufacturing testing for processors without any system performance, hardware or power consumption overheads.

My research interests also include On-Board Computers & Data Handling and On-Board Payload Data Processing Systems.

I am also involved in ESA PROBA-3 mission as WorkPackage (WP) Manager for the following WPs of the ASPIICS Coronagraph System Payload:
a) Image Data Compression IP Core NRE,
b) EM Image Data Compression IP Core Production, Validation and Test.

Currently, my research focuses on FPGA-based Hardware Acceleration for big streaming data workloads. Near the end of Dennard scaling, traditional performance and power scaling benefits based on technology scaling do not exist anymore. Moreover, transistor density improvements continue; the result is the “dark silicon” wall in which chips now have more transistors than a system can fully power at any point in time. To overcome these challenges, hardware acceleration in the form of datapath and control customized to particular algorithms or applications has surfaced as a promising solution. Hardware accelerators deliver orders of magnitude performance and energy benefits compared to traditional general purpose architecture solutions. Future computer architectures will be composed general purpose CPUs, GPUs, and hardware accelerators.

In this context, cutting-edge technology FPGA accelerators have been developed as IP Cores for image and data compression, channel coding and encryption, providing state-of-the-art data-rate performance, increased by orders of magnitude and at a fraction of power compared to general purpose CPUs.

Currently, there are more than 600 citations (excluding self-citations of all authors) that refer to his published material

The h-index (qualifies the impact and quantity of research output) for his research work is h-index = 15.

The Elsevier SCOPUS citation database reports 412 citations (excluding self-citations of all authors) and h-index =12
(https://www.scopus.com/authid/detail.uri?authorId=6603178443)

The Google Scholar database reports 818 citations and h-index =15 (https://scholar.google.gr/citations?user=ps8mOuMAAAAJ&hl)

Book Chapter

N. Kranitis, A. Paschalis. D. Gizopoulos, G. Xenoulis, “Software-Based Self-Testing of Embedded Processors”. Invited Book Chapter in “Processor Design. System-On-Chip Computing for ASICs and FPGAs”, J. Nurmi (Editor), Springer, June 2007, ISBN 978-1-4020-5529-4

Journals / Magazines

J1.  N. Kranitis, D. Gizopoulos, A. Paschalis, M. Psarakis and Y. Zorian, “Power/Energy Efficient Built-In Self-Test Schemes for Processor Datapaths”, IEEE Design & Test of Computers, Special Issue on Microprocessor Test and Verification, vol. 17, no. 4, pp. 15-28, October-December 2000

J2.  N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis and Y. Zorian, “An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths”, Springer Journal of Electronic Testing, Theory and Applications (JETTA) , vol. 17, pp. 97-107, April 2001

J3. N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Instruction-Based Self-Testing of Processor Cores”, Springer Journal of Electronic Testing: Theory and Applications (JETTA), Invited Paper, Special Issue on the 20th IEEE VLSI Test Symposium, vol. 19,  no. 2, pp. 103-112,  April 2003

J4.  N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Low-cost software-based self-testing of RISC processor cores”, IEE Proceedings – Computers and Digital Techniques, Invited Paper, Special Issue on the ACM/IEEE Design, Automation and Test in Europe Conference (DATE’03), vol. 150 , no. 5 , pp. 355-360, Sept. 2003

J5. I. Voyiatzis, N. Kranitis, D. Gizopoulos, A. Paschalis, C. Halatsis, “Accumulator-based built-in self-test generator for robustly detectable sequential fault testing”, IEE Proceedings – Computers and Digital Techniques, vol.151, no.6,  pp. 466-472, Nov. 2004

J6. I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, C. Halatsis, “A concurrent built-in self-test  architecture based on a self-testing RAM”, IEEE Transactions on Reliability, vol. 54,  no. 1,  pp. 69-78, March 2005

J7. N. Kranitis, A. Paschalis, D. Gizopoulos, G. Xenoulis, “Software-Based Self-Testing of Embedded Processors”, IEEE Transactions on Computers, vol. 54, no. 4,  pp. 461-475, April 2005

J8. N. Kranitis, A. Merentitis, G. Theodorou, A. Paschalis, D. Gizopoulos, “Hybrid-SBST Methodology for Efficient Testing of Processor Cores”, IEEE Design & Test of Computers, vol.25, no.1, pp.64-75, Jan-Feb 2008

J9. A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos, “Low Energy On-Line Self-Test of Embedded Processors in Dependable WSN Nodes”, IEEE Transactions on Dependable and Secure Computing, vol. 9, no. 1, pp. 86-100, Jan. – Feb. 2012

J10. G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “Software-Based Self-Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures”, IEEE Transactions on Very Large Scale Integration Systems, vol.21, no.4, pp.786-790, April 2013

J11. G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “Software-Based Self-Test for Small Caches in Microprocessors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 12, pp. 1991-2004, December 2014

 J12. N. Kranitis, I. Sideris, A. Tsigkanos, G. Theodorou, A. Paschalis, R. Vitulli, “An Efficient FPGA Implementation of CCSDS 121.0-B-2 Lossless Data Compression algorithm for Image Compression”, Journal of Applied Remote Sensing (JARS), Volume 9, Issue 1, Special Issue on Onboard Compression and Processing for Space Data Systems, May 2015

J13. A. Tsigkanos, N. Kranitis, G. Theodorou, A. Paschalis, “A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA”, IEEE Transactions on Emerging Topics in Computing, SI: Advanced Command, Control and On-Board Data Processing for Space Avionic Systems, 2018 (doi: 10.1109/TETC.2018.2854412)

Conferences and Workshops

 C1. A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian. “An Effective BIST Architecture for Fast Multiplier Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 1999 (DATE’99), March 1999, pp.117-121

C2.  N. Kranitis, M. Psarakis, A. Paschalis, D. Gizopoulos, and Y. Zorian, “Built-In-Self-Test for Shifter – ALU pairs in Datapaths”, in Proceedings of the 5th IEEE On-Line Testing Workshop (IOLTW’99), July 1999, pp. 92-96

C3.  D. Gizopoulos, M. Psarakis, A. Paschalis, N. Kranitis and Y. Zorian, “Low Power Built-In Self-Test for Datapath Architectures”, in Proceedings of the 2nd IEEE International Workshop on Microprocessor Test and Verification (MTV’99), Oct. 1999

C4.  M. Psarakis, N. Kranitis, D. Gizopoulos, A. Paschalis, and Y. Zorian “Deterministic Built-In Self-Test for Shifters, Adders and ALUs in Datapaths”, in Proceedings of the 1st IEEE Latin-American Test Workshop (LATW’00), March 2000  

C5.  D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y. Zorian, “Effective Low Power BIST for Datapaths”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2000 (DATE’00), March 2000, p.757 (poster)

C6.  D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y. Zorian. “Low Power/Energy BIST Scheme for Datapaths”, in Proceedings of the 18th IEEE VLSI Test Symposium (VTS’00), April 2000, pp. 23-28

C7. A. Paschalis, N. Kranitis, D. Gizopoulos, M. Psarakis, Y. Zorian, “Effective Deterministic Arithmetic BIST Architecture for Embedded Processor Cores”, in Proceedings of the 4th IEEE International Workshop on Testing Embedded Core-based System-Chips (TECS’00), May 2000

C8. A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian, “Deterministic Software-Based Self-Testing of Embedded Processor Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2001 (DATE’01), Munich, March 2001, pp. 92-96

C9. N. Kranitis, M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian, “An effective deterministic BIST scheme for Shifter/Accumulator pairs in datapaths”, in Proceedings of the 2nd IEEE International Symposium on Quality Electronic Design (ISQED’01), March 2001, pp. 343-349

C10. M. Psarakis, D. Gizopoulos, A. Paschalis, N. Kranitis and Y. Zorian, “Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers”, in Proceedings of the 19th IEEE VLSI Test Symposium (VTS’01), April 2001, pp. 15-20

C11. N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Effective Software Self-Test Methodology for Processor Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2002 (DATE’02), March 2002, pp. 592-597

C12. N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Instruction-Based Self-Testing of Processor Cores”, in Proceedings of the 20th IEEE VLSI Test Symposium (VTS’02), April 2002, pp.223-228

C13. Y. Voyiatzis, N. Kranitis, A. Paschalis, D. Gizopoulos, C. Halatsis, “ALU-based Built-In Self Test Generator for Transition Fault Testing”, in Proceedings of the 7th IEEE European Test Workshop (ETW’02), May 2002

C14. G. Xenoulis, N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Embedded Software-Based Self-Testing of Processor Cores: Application to a RISC Architecture”, in Proceedings of the 3rd IEEE International Workshop on Test Resource Partitioning (TRP02), October 2002

C15. N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Software-Based Self-Testing of Large Register Banks in RISC Processor Cores”, in Proceedings of the 4th IEEE Latin-American Test Workshop (LATW’03), January 2003

C16. N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Low-Cost Software-Based Self-Testing of RISC Processor Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2003 (DATE’03), March 2003, pp. 714-719 (Best Paper Award Nomination)

C17. G. Xenoulis, D. Gizopoulos, N. Kranitis, A. Paschalis, “Low-Cost On-Line Software-Based Self-Testing of Embedded Processor Cores”, in Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS’03), July 2003, pp.149-154

C18. N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores”, in Proceedings of the IEEE International Test Conference 2003 (ITC’03), October 2003, pp. 431-440

C19.  N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, C. Halatsis, “Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2006 (DATE’06), March 2006, pp. 65-70

C20. P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis, “A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs”, in Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS’06), July 2006, pp. 235-241

C21. A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos, “Selecting Power-Optimal SBST Routines for On-Line Processor Testing”, in Proceedings of the 12th IEEE European Test Symposium (ETS’07), May 2007, pp.111-116

C22. A. Merentitis, G. Theodorou, M. Giorgaras, N. Kranitis, “Directed Random SBST Generation for On-Line Testing of Pipelined Processors”, in Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS’08), July 2008, pp. 273-279

C23. A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos, “Low Energy On-Line SBST of Embedded Processors”, in Proceedings of the IEEE International Test Conference (ITC 2008), October 2008, paper 12.1

C24. G. Theodorou, N. Kranitis, A. Paschalis, D.Gizopoulos, “A SBST Methodology for applying March Test to Processor Cache Memory Tags”, Digest of Papers of the 14th IEEE European Test Symposium (ETS’09), May 2009

C25.  G. Theodorou, N.Kranitis, A. Paschalis, D. Gizopoulos, ” A Software-Based Self-Test Methodology for In-System Testing of Processor Cache Tag Arrays”, in Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS’10), July 2010, pp. 159-164

C26. A. Merentitis, D. Margaris, N. Kranitis, A. Paschalis, D. Gizopoulos, ” SBST for On-Line Detection of Hard Faults in Multiprocessor Applications Under Energy Constraints”, in Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS’10), July 2010, pp. 62-67

C27. A. Merentitis, A. Paschalis, D. Gizopoulos, N. Kranitis, “Energy Optimal On-Line Self-Test of Microprocessors in WSN Nodes”, in Proceedings of the 28th IEEE International Conference on Computer Design, (ICCD 2010), October 2010

C28. G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, ” A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches”, in Proceedings of the IEEE International Test Conference (ITC 2011), September 2011, paper 10.1

C29. G. Theodorou, S. Chatzopoulos, N. Kranitis, A. Paschalis, D. Gizopoulos,  “A Software-Based Self-Test methodology for on-line testing of data TLBs,” in Proceedings of the 17th IEEE European Test Symposium (ETS), 2012, May 2012

C30. J.-Y. Plesseria et al, “Design and Development of ASPIICS, an Externally Occulted Solar Coronagraph for PROBA-3 Mission”, in Proceedings of the 5th International Conference on Spacecraft Formation Flying Missions and Technologies (SFFMT), May 2013

C31. A. Paschalis, N. Kranitis, G. Theodorou, A. Poulakidas, G. Haritakis, D. Habas, P. Levacher, W. Curdt, H. Michalik, B. Fiethe, K. Tsinganos, C. Gontikakis, J.-Y. Plesseria, “ASPIICS CCB: The Functional Control Electronics of an Externally Occulted Solar Coronagraph Instrument for the ESA PROBA-3 Mission”, in Proceedings of the 5th International Conference on Spacecraft Formation Flying Missions and Technologies (SFFMT), May 2013

C32. E. Renotte et al, “ASPIICS: an externally occulted coronagraph for PROBA-3. Design evolution”, in Proceedings of the SPIE Astronomical Telescope and Instrumentation 2014, June 2014

C33. G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “Power-Aware Optimization of Software-Based Self-Test for L1 Caches in Microprocessors”, in Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS’14), July 2014

C34.  A. Paschalis, H. Michalik, N. Kranitis, C. López-Ongil, P. Reviriego Vasallo, “Dependable Reconfigurable Space Systems: Challenges, New Trends and Case Studies”, in Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS’14), July 2014

C35. N. Kranitis, G.Theodorou, A. Tsigkanos, A.Paschalis, R.Vitulli, “A Reconfigurable FPGA Implementation of CCSDS 122.0-B-1 Image Data Compression for ESA PROBA-3 Coronagraph System Payload”, in the Proc. of the On-Board Payload Data Compression (OBPDC) Workshop, October 2014

C36. I. Sideris, N. Kranitis, G.Theodorou, A. Tsigkanos, A.Paschalis, R.Vitulli, “A Reconfigurable FPGA Implementation of CCSDS 121.0-B-2 Lossless Data  Compression”, in the Proc. of the On-Board Payload Data Compression (OBPDC) Workshop, October 2014

C37. N. Kranitis, A. Tsigkanos, G. Theodorou, I. Sideris, A. Paschalis, “A Single Chip Dependable and Adaptable Payload Data Processing Unit”, in Proceedings of the 21th IEEE International On-Line Testing Symposium (IOLTS’15), July 2015

C38. N. Kranitis, G. Theodorou, A. Tsigkanos, A. Paschalis, “High Performance CCSDS Image Compression Implementations on Space-Grade SRAM FPGAs”, Space FPGA Users Workshop (SEFUW), 3rd Edition, 15-17 March 2016, European Space Research and Technology Centre (ESTEC), The Netherlands

C39.  D. Theodoropoulos, N. Kranitis, A. Paschalis, “An Efficient LDPC Encoder Architecture for Space Applications”, in Proceedings of the 22th IEEE International On-Line Testing Symposium (IOLTS’16), July 2016

C40.  G. Theodorou, N. Kranitis, A. Tsigkanos, A. Paschalis, “High Performance CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Implementation on a Space-Grade SRAM FPGA”, in Proceedings of the On-Board Payload Data Compression (OBPDC) Workshop, September 2016

C41. E. Renotte et al, “Design status of ASPIICS, an externally occulted coronagraph for PROBA-3”, Proceedings of SPIE – The International Society for Optical Engineering, Vol. 9604, August 2015

C42. E. Renotte et al, “Recent achievements on ASPIICS, an externally occulted coronagraph for PROBA-3”, Proceedings of SPIE – The International Society for Optical Engineering, Vol. 9904, July 2016

C43 A. Tsigkanos, N. Kranitis, A.Paschalis, “CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Implementation on a Next-Generation Space-Grade SRAM FPGA”, in the Proc. of the On-Board Payload Data Compression (OBPDC) Workshop, September 2018

• Member of the Institute of Electrical and Electronic Engineers (IEEE)
• Member of the IEEE Computer Society

Served as reviewer for several journals, magazines and conferences including:

• IEEE Transactions on Computers
• IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• IEEE Transactions on Circuits and Systems
• IEEE Design & Test of Computers
• IEEE Communications
• IEEE Geoscience and Remote Sensing Letters
• IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
• Springer Journal of Electronic Testing: Theory and Applications (JETTA)
• ACM/IEEE Design, Automation and Test in Europe (DATE) Conference
• IEEE International Test Conference (ITC)
• IEEE VLSI Test Symposium (VTS)
• IEEE European Test Symposium (ETS)
• IEEE International On-Line Testing Symposium (IOLTS)

Served as member of Program and Organizing Committee:

• Program Committee Member IEEE International On-Line Testing Symposium (IOLTS) 2015
• Program Committee Member IEEE International On-Line Testing Symposium (IOLTS) 2014
• Program Committee Member and Finance Chair, IEEE International On-Line Testing Symposium (IOLTS) 2013
• Finance Chair, IEEE International On-Line Testing Symposium (IOLTS) 2010
• Finance Chair, IEEE International On-Line Testing Symposium (IOLTS) 2008
•  Local Chair IEEE International On-Line Testing Symposium (IOLTS) 2007
•  Finance Chair, IEEE International On-Line Testing Symposium (IOLTS) 2003