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Antonis Paschalis

Professor in Logic Design and Architecture

Prof. Antonis Paschalis is full Professor in Logic Design and Architecture at the Dept. of Informatics & Telecommunications of the School of Science of the National and Kapodistrian University of Athens. Prior to that, he was Senior Researcher at Inst. of Informatics & Telecommunications of National Centre of Scientific Research “Demokritos”.

Prof. Paschalis is the director of the Digital Systems & Computer Architecture Laboratory (DSCAL), the head of Digital Systems and Space System Design group, leading the participation of the team in the ESA’s PROBA-3 space mission. His current research interests are space electronics design, embedded system design and processor-based self-test, fault tolerant design and architecture. The last decade his research activities focus on Embedded Processor-Based Self-Test of Systems-on-Chips and Low Power/Energy On-Line Fault Detection for Processors Cores and Memories. He has published more than 130 scientific publications, he is author of  a book and he holds a US patent in the area of Built-In Self-Test. He has been involved in 14 R&D projects funded by the EU, the Greek government and the SARG of the UoA and has been the project leader of 8 of them, all in the area of design and test of computer and communication systems. He was member of the editorial board of Journal of Electronic Testing: Theory and Applications and he has served the international Design and Test community as vice chair of the Communications Group of the Test Technology Technical Council (TTTC) of the IEEE Computer Society and participated in several Organizing (7 times as General Chair), Steering and Program Committees of IEEE international events. Prof. Antonios Paschalis is a Golden Core Member of the IEEE Computer Society and he has supervised 6 graduated Ph.D. students, 5 of them have made career in academia.

Contact

Email: paschalis at di dot uoa dot gr
Phone: +30 210 7275231
Office: 1st floor, Office A39
Mailing Address:
National and Kapodistrian University of Athens,
Dept. of Informatics and Telecommunications,
Panepistimiopolis, Ilissia
Athens 15784, Greece

Education

Ph.D. in Computers (1987) Dept. of Physics, University of Athens
Thesis title: “Totally Self-Checking Microprogrammed Control Units for High Reliable Computers”
M.Sc. in Electronics and Computers (1986), Physics Department, University of Athens
B.Sc. in Physics (1983) Dept. of Physics, University of Athens, Greece

Teaching

Undergraduate courses (Dept. of Informatics & Telecommunications, University of Athens, Greece)

  • Logic Design (Fall 1999 – today)
  • Computer Architecture I (Fall 2000, Fall 2001, Fall 2002, Fall 2003)
  • Design of Digital Systems (Spring 2001 – today)

Postgraduate courses (Dept. of Informatics & Telecommunications, University of Athens, Greece)

  • Advanced Design of Digital Systems (Spring 1999 – today)     VLSI  Testing  (Spring 2003 – 2009)
Research Interests
  • Space electronics
  • On-Board Computers & Data Handling
  • On-Board Payload Data Processing Systems
  • Embedded Processor-Based Self-Test of Systems-on-Chips     
  • Logic/RTL Design and Architecture of Digital Systems based on DFT and BIST Techniques
  • Low Power/Energy Processor and Memory On-Line Fault Detection and Reliability
  • Fault Tolerant Design and Architectures
Honors and Awards
  • “Golden Core Member” from I.E.E.E. Computer Society in 2005
  • “Meritorious Service Award” from I.E.E.E. Computer Society in 2007, “for significant services to the IEEE On-line Test Symposium during the past ten years”.   
  • “Meritorious Service Award” from I.E.E.E. Computer Society in 2005, “for providing leadership to the European Test Workshop/Symposium in the past decade and significant services as General Chair in 2002”.  
  • “Certificate of Appreciation” from I.E.E.E. Computer Society in 1999, “for serving as co-chair of the IEEE On-line Test Workshop and Providing 5 years of service on the Workshop Committee”. 
  • “Certificate of Appreciation” from I.E.E.E. Computer Society in 2002, “for serving as General co-chair of the IEEE European Test Workshop”.    
  • “Certificate of Appreciation” from I.E.E.E. Computer Society in 2003, “for serving the TTTC as fringe meetings chair”.
Citations / h-Index

His research work has achieved remarkable international acknowledgment from other researchers. Currently, there are more than 1300 citations that refer to his published material

The h-index (qualifies the impact and quantity of  research output) for his research work is h-index = 22

Professional Service / Memberships
  • Member of Εditorial Board of Journal of Electronic Testing: Theory and Applications (1996 – 2005)
  • Vice-Chair of Communication Group of Test Technology Technical Committee (TTTC) (2000 – today)
  • Member of Steering Committee of IEEE European Test Symposium/Workshop (2002 – 2006)
  • Member of European Test Technology Technical Committee (ETTTC) (1996 – today)
  • ΕΤΤΤC Contact Person for Greece (2002 – today)
  • General co-Chair of the 3rd IEEE International On-Line Testing Workshop, 1997.
  • General co-Chair of the 5th IEEE International On-Line Testing Workshop, 1999.
  • General co-Chair of the 13th IEEE International On-Line Testing Symposium, 2007.
  • General co-Chair of the 14th IEEE International On-Line Testing Symposium, 2008.
  • General co-Chair of the 16th IEEE International On-Line Testing Symposium, 2010.
  • General co-Chair of the 17th IEEE International On-Line Testing Symposium, 2011.
  • General co-Chair of the 19th IEEE International On-Line Testing Symposium, 2013.
  • General co-Chair of the 7th IEEE European Test Workshop, 2002.
  • Vice-General co-Chair of the 9th IEEE International On-Line Testing Symposium, 2003.
  • Member of Program Committee in the following conferences:
    • IEEE International On-Line Testing Symposium /Workshop IOLTS/IOLTW) (1995 – today)
    • IEEE European Test Symposium/Workshop (ETS/ETW) (1996 – 2007)
    • IEEE VLSI Test Symposium (VTS) (1998 – 2005)
    • IEEE Design Automation and Test in Europe (DATE) Conference (1999 – 2011)
    • IEEE International symposium on Defect and fault Tolerance in VLSI Systems (DFT) (2008)
    • IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (2008)
    • EUROMICRO Symposium on Digital Systems Design (DSD) (1998 – 2001)
    • Member of Program Committee in Test Technology Educational Program (TTEP) (2000 – today)
    • Moderator in several conference sessions
Graduated PhD Students
  • D. Gizopoulos
    Graduated 1997. Thesis title: “Architectures of Iterative Logic Arrays in CMOS VLSI Technology with Design for Testability Techniques”
    Current position: Professor, National and Kapodistrian University of Athens, Department of Informatics and Telecommunications
  •  T. Haniotakis
    Graduated 1998. Thesis title: “Design of Totally Self-Checking Circuits in VLSI Technology”
    Current position: Assistant Professor, University of Patras, Department of Computer Engineering and Informatics
  • I. Voyiatzis
    Graduated 1998. Thesis title: “Built-In Self-Test Architectures for Digital circuits in CMOS VLSI Technology”
    Current position: Application Professor, Technological Educational Institute of Athens, Department of Informatics
  • M. Psarakis
    Graduated 2002. Thesis title: “Efficient Test Techniques for Iterative Logic Arrays in CMOS VLSI Technology”
    Current position: Assistant Professor, University of Piraeus, Department of Informatics
  •  N. Kranitis
    Graduated 2005. Thesis title: “Effective Software-Based Self-Test Techniques for Processors”
    Current position: Senior Researcher, University of Athens, Department of Informatics & Telecommunications
  • A. Merentitis
    Graduated 2011. Thesis title: “A Reliability Optimized Methodology for High-Performance and Low-Power Processors in CMOS VLSI Technology”
    Current position: Senior Researcher, AGT International, Darmstadt, Germany
  • G. Theodorou
    Graduated 2012. Thesis title: “Fault Detection Methodology for Caches in Reliable Modern VLSI Microprocessors based on Instruction Set Architectures”
    Current position: Post Doc., University of Athens, Department of Informatics & Telecommunications
Publications

Book Chapters

“Embedded Processor-Based Self-Test”, D. Gizopoulos, A. Paschalis, Y. Zorian, Springer/Kluwer Academic Publishers, Dec. 2004, pages 217, ISBN 0-7923-8132-7.

“Concurrent Delay Testing in Totally Self-Checking Systems”, A. Paschalis, D. Gizopoulos and N. Gaitanis. Book series : Frontiers in Electronic Testing, Volume 11: On-Line Testing for VLSI, Chapter 2.4, Kluwer Academic Publishers, 1998, (selected set of articles).

“Software-Based Self-Testing of Embedded Processors”, N. Kranitis, A. Paschalis. D. Gizopoulos, G. Xenoulis, Invited Book Chapter in “Processor Design. System-On-Chip Computing for ASICs and FPGAs”, J. Nurmi (Editor), Springer, June 2007, ISBN 978-1-4020-5529-4, (invited chapter)

US Patent
  “A Built-In Self Test Method and Apparatus for Booth Multipliers”, D. Gizopoulos, A. Paschalis and Y. Zorian, United States Patent and Trademark Office, Patent number 5.960.009, Sept. 28, 1999.

IEEE Technical Journals, Magazines & Invited Publications (26)

 “Efficient Modular Design of TSC Checkers for M-out-of-2M Codes” A. M. Paschalis, D. Nikolos and C. Halatsis, IEEE Transactions on Computers, vol. 37, no. 3, March 1988, pp. 301-309.

“Efficient Design of Totally Self-Checking Checkers for All Low-Cost Arithmetic Codes”. D. Nikolos, A. Paschalis and G. Philokyprou, IEEE Transactions on Computers, vol. 37, no. 7, July 1988, pp. 807-814.

“An Efficient TSC 1-out-of-3 Code Checker”, A.M. Paschalis, C. Efstathiou, and C. Halatsis, IEEE Transactions on Computers, Vol. 39, No. 3, March 1990, pp. 407-411.

“On TSC Checkers for M-out-of-N Codes”, V. Dimakopoulos, G. Sourtziotis, A. Paschalis and D. Nikolos. IEEE Transactions on Computers, vol. 44, Aug. 1995, pp. 1055-1059.

“Efficient Totally Self-Checking Checkers for a Class of Borden Codes”, Th. Haniotakis, A.M. Paschalis, and D. Nikolos, IEEE Transactions on Computers, vol. 44, Nov. 1995, pp. 1318-1322.

“Effective Built-In Self-Test for Booth Multipliers”, D. Gizopoulos, A. Paschalis and Y. Zorian. IEEE Design & Test of Computers, vol. 15, no. 3, 1998, pp. 105-111.

“An Effective Built-In Self-Test Scheme for Array Multipliers”, D. Gizopoulos, A. Paschalis and Y. Zorian. IEEE Transactions on Computers, vol. 48, no. 9, Sept. 1999, pp. 936-950.

“Power/Energy Efficient Built-In Self-Test Schemes for Processor Datapaths”, N. Kranitis, D. Gizopoulos, A. Paschalis, M. Psarakis and Y. Zorian, IEEE Design & Test of Computers, Special Issue on Microprocessor Test and Verification, vol. 17, no. 4, Oct 2000, pp. 15-28.

“Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays”, M. Psarakis, D. Gizopoulos, A. Paschalis, and Y. Zorian, IEEE Transactions on Computers, vol. 49, no. 10, Oct. 2000, pp. 1083-1099.

“Instruction-Based Self-Testing of Processor Cores”, N.Kranitis, A.Paschalis, D.Gizopoulos, Y.Zorian, Journal of Electronic Testing: Theory and Applications, VTS 2002 Special Issue, Invited Paper, vol. 19, no 2, pp. 103-112, April 2003.

“Low-Cost Software-Based Self-Testing of RISC Processor Cores”, N.Kranitis, Y.Xenoulis, D.Gizopoulos, A.Paschalis, Y.Zorian, IEE Proceedings Computers & Digital Techniques, DATE’03 Special Issue, Invited Paper, vol. 150, no. 5, 2003.

“Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors”, A. Paschalis, D. Gizopoulos, IEEE Transactions on CAD of Integrated Circuits and Systems, DATE’04 Special Issue, Invited Paper, vol. 24, no.1, pp. 88-99, Jan. 2005.

“A Concurrent Built-In Self-Test Architecture Based on a Self-Testing RAM”, I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis,    C. Halatsis, IEEE Transactions on Reliability, vol. 54, no. 1, pp. 69-78, March 2005.

“Built-In Sequential Fault Self-Testing of Array Multipliers”, M. Psarakis, D. Gizopoulos, A. Paschalis, IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 24, no. 3, pp. 449-460, March 2005.

“Software-Based Self-Testing of Embedded Processors”, N. Kranitis, A. Paschalis, D. Gizopoulos, G. Xenoulis, IEEE Transactions on Computers, vol. 54, no.4, pp. 461-475, April 2005.

“Accumulator-Based Test Generation for Robust Sequential Fault Testing in DSP Cores in Near-Optimal Time”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no.9, pp. 1079-1086, Sept 2005.

“Testability Analysis and Scalable Test Generation for High-Speed Floating Point Units”, G.Xenoulis, D.Gizopoulos, M.Psarakis and A.Paschalis, IEEE Transactions on Computers, vol. 55, no. 11, Nov. 2006, pp. 1449-1457.

“Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip”, A. Apostolakis, M. Psarakis, D. Gizopoulos, A. Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 8, pp. 971-975, Aug. 2007.

“Hybrid Software-Based Self-Test (H-SBST): Methodology and Application on a Modern Processor Core,” N. Kranitis, A. Merentitis, G. Theodorou, A. Paschalis, D. Gizopoulos, IEEE Design & Test of Computers, vol.25, no.1, pp.64-75, Jan-Feb 2008.

“An Input Vector Monitoring Concurrent BIST Architecture Based on a Pre-computed Test Set”, I. Voyiatzis, A. Paschalis, D. Gizopoulos, C. Halatsis, E. Marki, M. Hatzimihail, IEEE Transactions on Computers, vol.57, issue 8, pp.1012-1022, Aug. 2008.

“Systematic Software-Based Self-Test for Pipelined Processors”, D.Gizopoulos, M.Psarakis, M.Hatzimihail, M.Maniatakos, A.Paschalis, A.Raghunathan, S.Ravi, IEEE Transactions on Very Large Scale Integration Systems, vol. 16, pp. 1441-1453, Nov. 2008.

“Instruction-based On-line Periodic Self-testing of Microprocessors with Floating-point Units”, G. Xenoulis, D. Gizopoulos, M. Psarakis, A. Paschalis, IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 2, pp. 124-134, April-June 2009.

“Recursive Pseudo-Exhaustive Two-pattern Generation”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 1, pp. 142-152, Jan. 2010.

“Low Energy On-Line Self-Test of Embedded Processors in Dependable WSN Nodes” A. Merentitis, N. Kranitis, A. Paschalis, D.Gizopoulos, IEEE Transactions on Dependable and Secure Computing, vol. 9, no. 1, pp. 86-100, Jan-Feb. 2012.

“Accumulator based 3-Weight Pattern Generation”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 2, pp. 357-361, Feb. 2012

“A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches”, G.Theodorou, N.Kranitis, A.Paschalis, D.Gizopoulos, IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp.786-790, Apr. 2013.

JETTA Journals (8)

“An Efficient Built-In Self-Test Method for Robust Path Delay Fault Testing”, I. Voyiatzis, A. Paschalis, D. Nikolos and C. Halatsis, Journal of Electronic Testing: Theory and Applications , vol. 8, 1996, pp. 219-222.

“C-Testable Modified-Booth Multipliers”, D. Gizopoulos, D. Nikolos, A. Paschalis, and C. Halatsis, Journal of Electronic Testing: Theory and Applications, vol. 8, 1996, pp. 241-260.

“Concurrent Delay Testing in Totally Self-Checking Systems”, A. Paschalis, D. Gizopoulos and N. Gaitanis, Journal of Electronic Testing: Theory and Applications, Special issue on On-Line Testing, vol. 12, 1998, pp. 55-61.

“A Totally Self-Checking 1-out-of-3 Code Error Indicator”, A. Paschalis, N. Gaitanis, D. Gizopoulos and P. Kostarakis. Journal of Electronic Testing: Theory and Applications, vol.13, no. 1, Aug. 1998, pp. 61-66.

“Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools”, M. Psarakis, D. Gizopoulos, A. Paschalis. Journal of Electronic Testing, Theory and Applications, vol. 13, no. 3, Dec. 1998, pp. 315-319.

“Αccumulator-Based BIST Approach for Two-Pattern Testing”, I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis. Journal of Electronic Testing, Theory and Applications, vol. 15, no. 3, Dec. 1999, pp. 267-278.

“An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths”, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis and Y. Zorian, Journal of Electronic Testing, Theory and Applications, vol. 17, April 2001, pp. 97-107.

“Easily Testable Cellular Carry Lookahead Adders”, D.Gizopoulos, M.Psarakis, A.Paschalis, Y.Zorian, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers/IEEE Computer Society, vol. 19, no. 3, pp. 285-298, June 2003.

Other Journals (14)

“Concurrently Totally Self-Checking Microprogram Control Unit with Duplication of Microprogram Sequencer”, A. M. Paschalis, C. Halatsis and G. Philokyprou, Microprocessing and Microprogramming, Special Ιssue on Fault Tolerant Computing, May 1987, pp. 271-281. 

“New Design Method for Low-Cost TSC Checkers for 1-out-of-N and (N-1)-out-of-N Codes in MOS Implementation”, G. Laskaris, T. Haniotakis, A. Paschalis, and D. Nikolos, Inter. Journal of Electronics, Vol. 69, No. 6, 1990, pp. 805-817.

“Fast and Low Cost TSC Checkers for 1-out-of-N and (N-1)-out-of-N Codes in MOS Transistor Implementation”, T. Haniotakis, A. Paschalis and D. Nikolos, Inter. Journal of Electronics, Vol. 71, No. 5, 1991, pp. 781-791.

“Efficient PLA Design of TSC 1-out-of-N Code Checkers”, A.M. Paschalis, Inter. Journal of Electronics, Vol. 73, No. 3, 1992, pp. 471-484.

“Totally Self-Checking Checkers for Borden Codes”, Th. Haniotakis, D. Nikolos, A. Paschalis, D. Gizopoulos, Inter. Journal of Electronics, Vol. 76, No. 1, 1994, pp. 57-64.

“Efficient Structured Design of TSC M-out-of-N Code Checkers with N > 2M and M=2^k-1”, A. Paschalis, Inter. Journal of Electronics, Vol. 77, No. 2, 1994, pp. 251-257.

“Robust Test Generation for Transistor Stuck-Open Faults in CMOS Complex Gates”, Y. Tsiatouhas, A. Paschalis, D. Nikolos, and C. Halatsis, International Journal of Electronics, vol. 79, no. 2, 1995, pp. 129-142.

“Linear-Testable and C-Testable Nx x Ny Modified Booth Multipliers”, D. Gizopoulos, A. Paschalis, D. Nikolos, and C. Halatsis, IEE Proceedings – Computers and Digital Techniques, vol. 143, no. 1, Jan. 1996, pp. 44-48.

“Fast C-Testable Array Multipliers”, D. Gizopoulos, D. Nikolos, and A. Paschalis, Inter. Journal of Electronics, vol. 80, no. 4, 1996, pp. 561-582.
“Testing CMOS Combinational Iterative Logic Arrays for Realistic Faults”, D. Gizopoulos, D. Nikolos, and A. Paschalis. Integration, the VLSI Journal, vol. 21, issue 3, Dec. 1996, pp. 209-228.

“Hierarchical Robust Test Generation for CMOS Circuit Stuck-Open Faults”, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, A. Paschalis, and C. Halatsis. International Journal of Electronics, vol. 82, no. 1, 1997, pp. 45-60.

“Testable Designs of One-Count Generators”, Th. Haniotakis, A. Paschalis, C. Halatsis and G. Philokyprou. International Journal of Electronics, vol. 85, no. 5, 1998, pp. 629-650.

“On Robust Two-Pattern Testing of One-Dimensional CMOS Iterative Logic Arrays”, D. Gizopoulos, A. Paschalis, D. Nikolos and C. Halatsis. International Journal of Electronics, vol. 86, no. 8, Aug. 1999, pp. 967-978.

“Accumulator-Based Built-In Self-Test Generator for Robustly Detectable Sequential Fault Testing”, I. Voyiatzis, N. Kranitis, D. Gizopoulos,    A. Paschalis, C. Halatsis, IEE Proceedings Computers & Digital Techniques, vol. 151, no. 6, 2004.

Selected Conference Publications (33)

“Αccumulator-Based BIST Approach for Stuck-Open and Delay Testing”, I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis. Proc. of the IEEE European Design and Test Conference 1995, March 1995, Paris, France, pp. 431-435.

“Testing Combinational Iterative Logic Arrays for Realistic Faults”, D. Gizopoulos, D. Nikolos, and A. Paschalis, Proc. of the 13th IEEE VLSI Test Symposium (VTS’95), May 1995, Princeton, USA, pp. 35-40.

“An Effective BIST Scheme for Booth Multipliers”, D. Gizopoulos, A. Paschalis, and Y. Zorian. Proc. of the IEEE International Test Conference 1995 (ITC’95), Washington, USA, Oct. 1995, pp. 824-833.

“An Asynchronous Totally Self-Checking Two-Rail Code Error Indicator”, N. Gaitanis, D. Gizopoulos, A. Paschalis and P. Kostarakis. Proc. of the 14th IEEE VLSI Test Symposium (VTS’96), May 1996, Princeton, USA, pp. 151-156.

“An Effective BIST Scheme for Datapaths”, D. Gizopoulos, A. Paschalis and Y. Zorian, Proc. of the IEEE International Test Conference 1996 (ITC’96), Oct. 1996, Washington, USA, pp. 76-85.

“A Totally Self-Checking 1-out-of-3 Code Error Indicator”, A. Paschalis, N. Gaitanis, D. Gizopoulos and P. Kostarakis. Proc. of the ΙΕΕΕ European Design & Test Conference 1997 (ED&TC’97), March 1997, Paris, France, pp. 450-454.

“Robust Sequential Fault Testing of Iterative Logic Arrays”, D. Gizopoulos, M. Psarakis, A. Paschalis. Proc. of the 15th IEEE VLSI Test Symposium (VTS’97), April 1997, Monterey, USA, pp. 238-244.

“An Effective BIST Scheme for Arithmetic Logic Units”, D. Gizopoulos, A. Paschalis and Y. Zorian. Proc. of the IEEE International Test Conference 1997 (ITC’97), 1997, Washington, USA, pp. 868-877.

“Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model”, M. Psarakis, D. Gizopoulos, A. Paschalis and Y. Zorian, Proc. of the 16th IEEE VLSI Test Symposium (VTS’98), Monterey, USA, April 1998, pp. 152-157.

“R-CBIST: An Effective RAM-based Input Vector Monitoring Concurrent BIST Technique”, I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis, Proc. of the IEEE International Test Conference 1998 (ITC’98), Washington, USA, pp. 918-925.

“An Effective BIST Architecture for Fast Multiplier Cores”, A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian. Proc. of the IEEE Design, Automation and Test in Europe Conference 1999 (DATE’99), March 1999, Munich, pp.117-121.

“An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers”, M. Psarakis, A. Paschalis, D. Gizopoulos, and Y. Zorian. Proc. of the 17th IEEE VLSI Test Symposium (VTS’99), April 1999, Dana Point, USA, pp. 252-258.

“Effective Low Power BIST for Datapaths”, D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y. Zorian. Proc. of the IEEE Design, Automation and Test in Europe Conference 2000 (DATE’00), March 2000, Paris, poster, p.757.

“Low Power/Energy BIST Scheme for Datapaths”, D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y. Zorian. Proc. of the 18th IEEE VLSI Test Symposium (VTS’00), April 2000, Montreal, Canada, pp. 23-28.

“Deterministic Software-Based Self-Testing of Embedded Processor Cores”, A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian, Proc. of the IEEE Design, Automation and Test in Europe Conference 2001 (DATE’01), March 2001, Munich, pp. 92-96.

“Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers”, M. Psarakis, D. Gizopoulos, A. Paschalis, N. Kranitis and Y. Zorian. Proc. of the 19th IEEE VLSI Test Symposium (VTS’01), April 2001, USA, pp. 15-20.

“Effective Software Self-Test Methodology for Processor Cores”, N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian, Proc. of the IEEE Design, Automation and Test in Europe Conference 2002 (DATE’02), March 2002, Paris, France, pp. 592-597.

“Instruction-Based Self-Testing of Processor Cores”, N. Kranitis, D. Gizopoulos, A. Paschalis, and Y. Zorian. Proc. of the 20th IEEE VLSI Test Symposium (VTS’02), April 2002, Monterey, USA, pp. 223-228.

“Low-Cost Software-Based Self-Testing of RISC Processor Cores”, N.Kranitis, Y.Xenoulis, D.Gizopoulos, A.Paschalis, Y.Zorian, Proc. of the IEEE Design Automation and Test in Europe Conference (DATE’2003), Munich, Germany, March 2003, pp. 714-719. (Best paper award nomination).

“Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores”, N.Kranitis, G.Xenoulis, A.Paschalis, D.Gizopoulos, Y.Zorian, Proc. of the IEEE International Test Conference 2003 (ITC’03), October 2003, USA.

“Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors”, A. Paschalis, D. Gizopoulos, Proc. of the IEEE Design Automation and Test in Europe Conference (DATE’2004), Paris, France, March 2004. (Best paper award nomination).

“A Concurrent BIST Scheme for Online/Offline Testing Based on a Precomputed Test Set”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, C. Halatsis, Proc. of the IEEE International Test Conference 2005 (ITC’05), pp. 215-220, USA, Nov. 2005.

“Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications”, N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, C. Halatsis, Proc. of the IEEE Design Automation and Test in Europe Conference (DATE’2006), Germany, March 2006.

“Systematic Software-Based Self-Test for Pipelined Processors”, M.Psarakis, D.Gizopoulos, M.Hatzimihail, A.Paschalis, A.Raghunathan, S.Ravi, ACM/IEEE Design Automation Conference (DAC’ 2006), San Fransisco, CA, USA, July 2006.

“Selecting Power-Optimal SBST Routines for On-Line Processor Testing”, A.Merentitis, N. Kranitis, A. Paschalis, D.Gizopoulos, IEEE European Test Symposium 2007 (ETS/07), Germany, May 2007.

“A Methodology for Detecting Performance Faults in Microprocessor Speculative Execution Units via Hardware Performance Monitoring”, M.Hatzimihail, M.Psarakis, D.Gizopoulos, A.Paschalis, IEEE International Test Conference (ITC 2007), Santa Clara, California, USA, October 2007.

“Functional Self-Testing for Bus-Based Symmetric Multiprocessors”, A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis, in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE’2008), Munich, Germany, March 2008.

“Low Energy On-Line SBST of Embedded Processors”, A.Merentitis, N. Kranitis, A. Paschalis, D.Gizopoulos, Proc. of the IEEE International Test Conference 2008 (ITC’08), USA, October, 2008.

“Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors”, A. Apostolakis, M. Psarakis, D. Gizopoulos, A. Paschalis, I. Parulkar, IEEE European Test Symposium (ETS 2009), pp. 33-38, Sevilla, Spain, May 2009.

“Energy Optimal On-Line Self-Test of Microprosessors in WSN Nodes”, A. Merentitis, A. Paschalis, D. Gizopoulos, and N. Kranitis, in Proc. of the International Conference on Computer Design (ICCD), pp. 376-383, 2010.

“A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches”, G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, Proc. of the IEEE International Test Conference 2011 (ITC’11), USA, September, 2011.

“Design and Development of ASPIICS, an Externally Occulted Solar Coronagraph for PROBA-3 Mission”, J.-Y. Plesseria, P. Levacher, W. Curdt, S. Vives, C. Guillon, A. Mazzoli, F. Rouesnel, A. Paschalis, N. Kranitis, A. Poulakidas, B. Fiethe, S. Shestov, S. Gunar, G. Capobianco, P. Lamy, P. Rochus, K. Tsinganos, S. Kuzin, P. Heinzel, S. Fineschi and the ASPIICS team, Proc. of the 5th International Conference on Spacecraft Formation Flying Missions and Technologies, Munich, Germany, May 2013.

“ASPIICS CCB: The Functional Control Electronics of an Externally Occulted Solar Coronagraph Instrument for the ESA PROBA-3 Mission”, A. Paschalis, N. Kranitis, G. Theodorou, A. Poulakidas, G. Haritakis, D. Habas, P. Levacher, W. Curdt, H. Michalik, B. Fiethe, K. Tsinganos, C. Gontikakis, J.-Y. Plesseria and the ASPIICS team, Proc. of the 5th International Conference on Spacecraft Formation Flying Missions and Technologies, Munich, Germany, May 2013.

Other Conference Publications (55)

“Efficient Modular Design of TSC Checkers for M-out-of-2M Codes”, A. M. Paschalis, D. Nikolos and C. Halatsis, (edited by F. Makedon, K. Mehlhorn, T. Papatheodorou and P. Spirakis), VLSI Algorithms and Architectures, Lecture Notes in Computer Science, vol. 227, Springer-Verlag, 1986, pp. 144-155.

“A Fault Tolerant Dynamic RAM Memory System”, D. Nikolos, P. Kostarakis and A. M. Paschalis, (edited by S. Tzafestas, M. Singh, and G. Schmidt), System Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, Vol. 2, D. Reidel Publishing Company, 1987, pp.301-308.

“Efficient Design of Totally Self-Checking Checkers for All Separate Low Cost Arithmetic Codes”, D. Nikolos, A. M. Paschalis and G. Philokyprou, (edited by S. Tzafestas, M. Singh, and G. Schmidt), System Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, Vol. 2, D. Reidel Publishing Company, 1987, pp. 345-356.

“Towards Concurrently Totally Self-Checking Microprogram Control Units”, A. M. Paschalis, C. Halatsis and G. Philokyprou, (edited by S. Tzafestas, M. Singh, and G. Schmidt), System Fault Diagnostics, Reliability and Related Knowledge-Based Approaches, Vol. 2, D. Reidel Publishing Company, 1987, pp. 357-368.

“Test and Verification Procedure Tool for Paralel Busses”, A. M. Paschalis, D. Marinakis, P. Kostarakis, and K. Dangakis, Proc. of the Eurobus/89 Conference, May 1989, Munich, pp. 226-233.

“Efficient Design of TSC Checkers for 1-Out-Of-N Codes in MOS Transistor Implementation”, G. B. Laskaris, T. N. Haniotakis, A. M. Paschalis, and D. Nikolos, Proc. of the 12th Inter. Conference of Fault- Tolerant Systems and Diagnostics, Praha, Sept. 1989, pp. 163-168.

“Data Busses (Fieldbus, VMEbus, Multibus II), K. Dangakis, N. Gaitanis, P. Kostarakis, D. Nikolos, and A. Paschalis, Proc. of the European Conference on Conformance Testing & Certification in Information Technology & Telecommunications, June 1990, Brussels, pp. 210-247.

“Totally Self-Checking Checkers for Optimal t-Unidirectional Error Detecting Codes, D. Nikolos, A.M. Paschalis, T.N. Haniotakis, and G.B. Laskaris, Proc. of the 13th Inter. Conference of Fault-Tolerant Systems and Diagnostics, Varna, June 1990, pp. 326-331.

“Neural Network Decoders for t-Error Correcting All Unidirectional Error Detecting Codes”, N. Gaitanis, D. Nikolos, and A.M. Paschalis, Proc. of the 13th Inter. Conference of Fault-Tolerant Systems and Diagnostics, Varna, June 1990, pp. 340-345.

“VMEbus Timing Protocol Conformance Testing”, A. Paschalis, K. Dangakis, P. Kostarakis, N. Gaitanis and L. Adilinis, Proc. of the Open Bus Systems ’91, Nov. 1991, Paris, pp. 113-120.

“A Conformance Test System for DECT Physical Layer”, A. Papavramidis, A. Paschalis, O. Myrtue, K. Dangakis, G. Tombras and P. Kostarakis, Proc. of the 3rd IEEE Inter. Symposium on Personal, Indoor and Mobile Radio Communications, Oct. 1992, Boston, Massachusetts, pp. 357-361.

“Development of a Conformance Test System for ERMES Receivers”, K. Dangakis, G. Tombras, A. Paschalis, A. Papavramidis and P. Kostarakis, Proc. of the 3rd IEEE Inter. Symposium on Personal, Indoor and Mobile Radio Communications, Oct. 1992, Boston, Massachusetts, pp.660-664.

“C-Testable Multipliers Based on the Modified Booth Algorithm”, D. Gizopoulos, D. Nikolos, A. Paschalis and P. Kostarakis. Proc. of the 3rd IEEE Asian Test Symposium (ATS’94), Nara, Japan, Nov. 1994, pp. 163-168.

“An Effective BIST Scheme for Booth Multipliers”, D. Gizopoulos, A. Paschalis, and Y. Zorian, 1995 IEEE BIST/DFT Workshop, March 1995.

“Test Procedures for DECT Physical Layer Conformance Testing”, A.A. Alexandridis, A. Paschalis, K. Dangakis, P. Kostarakis, F. Lazarakis, and N. Gaitanis, Proc. of the IEEE International Conference on Telecommunications, April 1995, pp. 106-109.

“BIST Synthesis for Booth Multipliers”, D. Gizopoulos, A. Paschalis, and Y. Zorian, 2nd IEEE International Test Synthesis Workshop (ITSW’95), May 1995, Santa Barbara, USA.

“Conformance Testing Measurements and Results on DECT Handsets”, A.A. Alexandridis, A. Paschalis, K. Dangakis, P. Kostarakis, F. Lazarakis, and S. Xiroutsikos, Proc. of the 5th International Conference on Advances in Communications & Control (COMCON 5), June 1995, pp. 684-694.

“Efficient Structured Design of Robustly Testable CMOS TSC M-out-of-2M Code Checkers”, Th. Haniotakis and A. Paschalis. Proc. of the 1st IEEE International On-Line Testing Workshop (IOLTW’95), July 1995, Nice, France, pp. 233-237.

“An Efficient BIST Scheme for Carry-Save and Carry-Propagate Array Multipliers”, D. Gizopoulos, A. Paschalis and Y. Zorian. Proc. of the 4th IEEE Asian Test Symposium (ATS’95), Nov. 1995, Bangalore, India, pp. 286-292.

“An Efficient Comparative Concurrent Built-In Self-Test Technique”, I. Voyiatzis, D. Nikolos, A. Paschalis, C. Halatsis, and Th. Haniotakis. Proc. of the 4th IEEE Asian Test Symposium (ATS’95), Nov. 1995, Bangalore, India, pp. 309-315.

“Totally Self-Checking Reconfigurable Duplication System with Separate Internal Fault Indication “, N. Gaitanis, P. Kostarakis and A. Paschalis. Proc. of the 5th IEEE Asian Test Symposium (ATS’95), Nov. 1995, Bangalore, India, pp. 316-321.

“A Totally Self-Checking Checker for All Cyclic AN Codes”, A. Paschalis, D. Gizopoulos, N. Gaitanis and P. Kostarakis, (edited by Y. Min and D. Tang), Computer-Aided Design, Test, and Evaluation for Dependability, International Academic Publishers, 1996, pp. 252-257.

“A New Totally Self-Checking Reconfigurable Duplication System”, N. Gaitanis, A. Paschalis, D. Gizopoulos, and P. Kostarakis, (edited by Y. Min and D. Tang), Computer-Aided Design, Test, and Evaluation for Dependability, International Academic Publishers, 1996, pp. 264-268.

“Conformance Testing Trials on ERMES Receivers”, P. Kostarakis, A. Alexandridis, K. Dangakis, A. Vlahakis, P. Katrivanos, F. Lazarakis, A. Paschalis and N. Gaitanis, (edited by B. Baumgarten, H.-J. Burkhardt and A. Giessler), Testing of Communicating Systems, Chapman & Hall, 1996, pp. 30-41.

“Deterministic BIST for Datapaths”, D. Gizopoulos, A. Paschalis and Y. Zorian. Proc. of the 1st IEEE European Test Workshop (ETW’96), France, May 1996.

“A Three-Rail Totally Self-Checking Error Indicator”, N. Gaitanis, P. Kostarakis and A. Paschalis. Proc. of the 2nd IEEE On-Line Testing Workshop (IOLTW’96), July 1996, France, pp. 50-52

“Concurrent Delay Detection in Duplication Systems”, A. Paschalis, D. Gizopoulos and N. Gaitanis. Proc. of the 2nd IEEE International On-Line Testing Workshop (IOLTW’96), July 1996, France, pp. 112-115.

“Integration of Test Procedures and Trials for DECT Handsets”, A Alonistioti, P. Kostarakis, K. Dangakis, A.A. Alexandridis, A. Paschalis, N. Gaitanis, S. Xiroutsikos, E. Adilinis, A. Vlahakis and P. Katrivanos, (edited by Myungchul Kim, Sungwon Kang, Keesoo Hong), Testing of Communicating Systems, Chapman & Hall, 1997, pp. 57-64.

“An Effective BIST Scheme for Carry Lookahead Adders”, D. Gizopoulos, A. Paschalis and Y. Zorian. Proc. of the 2nd IEEE European Test Workshop (ETW’97), Italy, May 1997.

“A Duplication System with Totally Self-Checking Reconfiguration Capability”, N. Gaitanis, A. Paschalis, D. Gizopoulos, P. Kostarakis, K. Dangakis, A. Alexandridis, A. Alonistioti. Proc. of the 3rd IEEE International On-Line Testing Workshop (IOLTW’97), 1997, Creta, Greece, pp. 141-145.

“Exhaustive and Pseudoexhaustive Arithmetic Built-In Two-Pattern Generation for Datapaths”, I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis. Proc. of the 4th IEEE On-Line Testing Workshop (IOLTW’98), July 1998, Capri, Italy, pp. 90-94.

“Mapping of SDL and CORBA Features for Modelling Software Radio Aspects”, A. Alonistioti, M. Koutsopoulou, G. Efthimiopoulos, A. Paschalis, Proc. of the 20th International Conference on Information Technology Interfaces (ITI’98), 1998, Croatia.

“Built-In-Self-Test for Shifter – ALU pairs in Datapaths”, N. Kranitis, M. Psarakis, A. Paschalis, D. Gizopoulos, and Y. Zorian. Proc. of the 5th IEEE On-Line Testing Workshop (IOLTW’99), July 1999, Rhodos, Greece, pp. 92-96.

“Efficient Design of Totally Self-Checking Checker – Decoders for all Cyclic AN codes”, A. Paschalis, D. Gizopoulos, M. Psarakis, and M. Nicolaidis. Proc. of the 5th IEEE On-Line Testing Workshop (IOLTW’99), July 1999, Rhodos, Greece, pp. 168-173.

“Low Power Built-In Self-Test for Datapath Architectures”, D. Gizopoulos, M. Psarakis, A. Paschalis, N. Kranitis and Y. Zorian, Proc. of the 2nd IEEE International Workshop on Microprocessor Test and Verification (MTV 99), Oct. 1999, USA.

“Application-oriented Microelectronics Education”, A. Paschalis and D. Gizopoulos, (edited by B. Courtois, N. Guillemot, G. Kamarinos, G. Stehelin), Microelectronics Education, Kluwer Academic Publishers, 2000.

“Deterministic Built-In Self-Test for Shifters, Adders and ALUs in Datapaths”, M. Psarakis, N. Kranitis, D. Gizopoulos, A. Paschalis, and Y. Zorian. Proc. of the 1st IEEE Latin-American Test Workshop, March 2000, Brasil.

“Effective Deterministic Arithmetic BIST Architecture for Embedded Processor Cores”, A.Paschalis, N.Kranitis, D.Gizopoulos, M.Psarakis, Y.Zorian, Proc. of the 4th IEEE International Workshop on Testing Embedded Core-based System-Chips (TECS’2000), Montreal, Canada, May 3-4, 2000.

“An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapath”, N. Kranitis, M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian, Proc. of the IEEE International Symposium on Quality Electronic Design 2001 (ISQED’01), March 2001, San Jose CA

“ALU-based Built-In Self Test Generator for Transition Fault Testing”, Y.Voyiatzis, N.Kranitis, A.Paschalis, D. Gizopoulos, C. Halatsis, 7th IEEE European Test Workshop (ETW’02), Corfu, Greece, May 2002, poster, pp. 23-24, Corfu, Greece.

“Embedded Software-Based Self-Testing of Processors Cores: Application to a RISC Architecture”, G.Xenoulis, N.Kranitis, D.Gizopoulos, A.Paschalis, Y.Zorian, IEEE International Test Resource Partitioning Workshop 2002 (TRP’2002), Baltimore, MD, USA, October 2002, pp. 2.2.1 – 2.2.5.

“Software-Based Self-Testing of Large Register Banks in RISC Processor Cores”, N.Kranitis, G.Xenoulis, D.Gizopoulos, A.Paschalis, Y.Zorian, S. Kazanjian, Proc. of the 4th IEEE Latin American Test Workshop 2003, Natal, Brazil, February 2003.

“Low-Cost On-Line Software-Based Self-Testing of Embedded Processor Cores”, G.Xenoulis, D.Gizopoulos, N.Kranitis, A.Paschalis, Proc. of the 9th IEEE International On-Line Testing Symposium 2003, Greece, July 2003, pp. 149-154.

“Accumulator-based Weighted Pattern Generation”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, 11th IEEE International On-Line Testing Symposium 2005, France, July 2005.

“Test Generation Methodology for High-Speed Floating Point Adders”, G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis, 11th IEEE International On-Line Testing Symposium 2005, France, July 2005.
“Software-Based self-Test for Pipelined Processors: A Case Study”, M. Hatzimihail, M. Psarakis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Proc. of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), pp. 535-543, USA, Oct. 2005.

“A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs”, P. Kenterlis, N. Kranitis, A. Paschalis, D.Gizopoulos, M.Psarakis, 12th IEEE International On-Line Testing Symposium 2006 (IOLTS 2006), Como, Italy, July 2006.

“A Functional Self-Test Approach for Peripheral Cores in Processor-based SoCs”, A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis, 13th IEEE International On-Line Testing Symposium 2007 (IOLTS 2007), Crete, Greece, July 2007.

“On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors”, G.Xenoulis, M.Psarakis, D.Gizopoulos, A.Paschalis, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 2007), Rome, Italy, September 2007.

“A Concurrent BIST Scheme Exploiting Don’t Care Values”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, IEEE/IFIP Symposium on VLSI-SoC 2008, Rhodes, Greece, October, 2008.

“A SBST Methodology for applying March Tests to Processor Cache Memory Tags”, G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, IEEE European Test Symposium (ETS 2009), Sevilla, Spain, May 2009, poster.

“An Input Vector Monitoring Concurrent BIST scheme Exploiting “X” values”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, 15th IEEE International On-Line Testing Symposium 2009 (IOLTS’09), Portugal, July 2009, poster.

“A software-based self-test methodology for in-system testing of processor cache tag arrays”, G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, 16th IEEE International On-Line Testing Symposium 2010 (IOLTS’10), Corfu, Greece, July 2010.

“SBST for On-Line Detection of Hard Faults in Multiprocessor Applications Under Energy Constraints”, A. Merentitis, D. Margaris, N. Kranitis, A. Paschalis, D. Gizopoulos, 16th IEEE International On-Line Testing Symposium 2010 (IOLTS’10), Corfu, Greece, July 2010.

“A Software-Based Self-Test Methodology for On-Line Testing of Data TLBs”, G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, IEEE European Test Symposium (ETS 2012), Annecy, France, May 2012, poster.