Digital Systems & Computer Architecture Laboratory (DSCAL) was established in 1999 as a research and education unit operating under the Sector of Computer Systems and Applications of the Department of Informatics & Telecommunications, University of Athens

The DSCAL is specialized in fault tolerant computing, dependable architectures, VLSI and processor testing, reconfigurable FPGA based Systems on Chip design and hardware implementation of image and data processing algorithms and has more than 25 years expertise in fault and radiation tolerant methodologies and more than 10 years expertise in Embedded Processor-Based Self-Test of Systems-on-Chips, while recently has developed a hardware/software platform for efficiently performing fault emulation experiments targeting SEEs in the configuration bits of Virtex FPGA devices, by utilizing run-time reconfiguration. DSCAL is currently working on the development of a reconfigurable image data compression unit of the Coronagraph System for the ESA PROBA‐3 space mission and has successfully completed the preliminary design phase of the Reconfigurable FPGA Image Data Compression IP Core under the ESTEC/Contract No. 4000106078.. 

DSCAL group is also actively involved in education. The undergraduate and graduate courses supported by the group include Logic Design, Computer Architecture (I and II), Design of Digital Systems, Advanced Computer Architecture, Advanced Design of Digital Systems.

AthenaRISC processor

AthenaRISC is a processor core developed at the Digital Systems & Computer Architecture Laboratory (DSCAL) of the Dept. of Informatics & Telecommunications, University of Athens, targeting academic and research applications. AthenaRISC closely resembles the processor described in the classic textbook on Computer Architecture by D.A. Patterson and J.L. Hennessy.

The current version of AthenaRISC processor (CPU core, Processor Verification and Test Suite and Processor Debug Suite) is described in this page.

OR1200 Processor Verification and Test Suite

OpenRISC processor Verification & Test Suite (OVTS) is developed for automatic functional verification and testing of OpenRISC 1200, a publicly available processor core that is released under the GNU Lesser General Public License.

current version of OpenRISC 1200 Processor Verification and Test Suite is described in this page.

Designed by: Panagiotis Kenterlis ©2007 - University of Athens - Department of Informatics & Telecommunications